The present invention relates generally to decoding architectures, and more particularly to fast, efficient architectures for inner and outer decoders that decode serially concatenated convolutional codes.
Digital communication systems employ coding for reliable data transmission over a noisy channel. This coding, while increasing reliability, forces the transmission data rate down. Claude Shannon, the founder of information theory, came up with bounds for the maximum rate that can be achieved when coding data while still maintaining reliable communication. Since then, much research has been done to achieve the bounds set out by Shannon's theory. One class of codes that comes very close to achieving Shannon's bound is turbo codes.
Turbo codes, conceived in 1993, have over time been split into two classes of codes: parallel concatenated convolutional codes (PCCC's) and serial concatenated convolutional codes (SCCC's). While both of these codes give excellent performance in terms of reliability, decoding such codes at the receiver proves to be a constant bottleneck in communication systems today, since these are very complex codes. Often, decoding of these codes also employs iterative techniques to lower the bit error rate (BER). Thus, speed is imperative when designing the decoder.
Algorithms using lookup tables and lower performance metrics have been conventionally used for SCCC decoder blocks. Examples of such algorithms are the well-known MAP algorithm and a less sophisticated Log-Max-MAP algorithm. Normalization is also a big problem in the state metric computation step, which can require significant computational complexity.
A paper “A Soft-Input Soft-Output Maximum A Posteriori (MAP) Module to Decode Parallel and Serial Concatenated Codes” by Benedetto et al. TDA Progress Report 24-27, Nov. 15, 1996 discloses a generalized SCCC decoder. The present invention improves upon this decoder design.
It would be desirable to have fast, efficient architectures for inner and outer decoders for use with serially concatenated convolutional codes. It would be desirable to have an improved architecture for inner and outer decoder blocks of an SCCC decoder that employs a Log-Max-MAP algorithm in a very efficient manner. It would be desirable to have an improved architecture for inner and outer decoder blocks that uses only add and compare operations, thus eliminating the need for lookup tables.